The speed of Very Large Scale Integration (VLSI) chips is increasingly limited by signal delay in long interconnect lines. In particular, with the progress of Integrated Circuit (IC) technology into the very deep submicron regime, signal propagation on long interconnects is becoming a major bottleneck in the performance of large circuits. For example, in memory devices, e.g., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc., data signals collected may be propagated from individual memory arrays to input/output (I/O) pads wherein the data may be made accessible to users.